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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m37470m2-xxxsp m37470m4-xxxsp m37470e4-xxxsp m37470m8-xxxsp m37470e8-xxxsp p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 reset v cc p1 6 /clk p1 5 /s out p1 4 /s in p1 3 / p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p1 7 /s rdy outline 32p4b t 1 p1 2 /t 0 description the 7470/7471 group is a single-chip microcomputer designed with cmos silicon gate technology. it is housed in a 32-pin shrink plastic molded dip. the m37471m2-xxxsp/fp is a single-chip mi- crocomputer designed with cmos silicon gate technology. it is housed in a 42-pin shrink plastic molded dip or a 56-pin plastic molded qfp. these single-chip microcomputer are useful for business equip- ment and other consumer applications. in addition to its simple instruction set, the rom, ram, and i/o addresses are placed on the same memory map to enable easy programming . the differences between the m37471m2-xxxsp and the m37471m2-xxxfp are the package outline and the power dissi- pation ability (absolute maximum ratings). the differences among m37470m2-xxxsp, m37470m4-xxxsp, m37470m8-xxxsp, m37471m2-xxxsp/fp, m37471m4-xxxsp/ fp and m37471m8-xxxsp/fp are noted below. application audio-visual equipment, vcr, tuner, office automation equipment 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers type name m37470m2-xxxsp m37471m2-xxxsp/fp m37470m4-xxxsp m37471m4-xxxsp/fp m37470m8-xxxsp m37471m8-xxxsp/fp i/o ports 26 36 26 36 26 36 rom size 4096 bytes 8192 bytes 16384 bytes ram size 128 bytes 192 bytes 384 bytes features l basic machine-language instructions ...................................... 71 l memory size rom ..................................................... 4096 bytes (m37471m2) ram ........................................................ 128 bytes (m37471m2) l the minimum instruction execution time ....................................... 0.5 m s (at 8 mhz oscillation frequency) l power source voltage .............. 2.7 to 4.5 v (at 2.2v cc C2.0 mhz oscillation frequency) ............................... 4.5 to 5.5 v (at 8 mhz oscillation frequency) l power dissipation in normal mode ................................... 35 mw (at 8.0 mhz oscillation frequency) l subroutine nesting ...... 64 levels max. (m37470m2, m37471m2) l interrupt ................................................... 12 sources, 10 vectors l 8-bit timers .................................................................................. 4 l programmable i/o ports (ports p0, p1, p2, p4) ......................................... 22(7470 group) 28(7471 group) l input port (port p3) ............................................... 4(7470 group) (ports p3, p5) ....................................... 8(7471 group) l serial i/o (8-bit) .......................................................................... 1 l a-d converter ............................... 8-bit, 4channels (7470 group) 8-bit, 8channels (7471 group) pin configuration (top view)
2 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pin configuration (top view) p1 3 /t 1 p1 2 /t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 m37471m2-xxxsp m37471m4-xxxsp m37471e4-xxxsp m37471m8-xxxsp m37471e8-xxxsp m37471e8ss 17 18 19 20 21 26 25 24 23 22 p5 3 p1 6 /clk p1 5 /s out p1 4 /s in p1 1 p1 0 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p1 7 /s rdy p5 2 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 3 p4 2 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 p5 1 /x cout p5 0 /x in v cc reset outline 42p4b 42s1b-a (window) p0 6 p1 5 /s out p2 1 /in 1 17 28 27 26 25 24 23 22 21 20 19 18 56 45 46 47 48 49 50 51 52 53 54 55 44 43 42 29 30 31 32 33 34 35 36 37 38 39 40 41 1 2 3 16 15 14 13 12 11 10 9 8 7 6 5 4 p5 2 p0 7 p0 5 p5 3 p1 6 /clk v ss nc nc nc p1 7 /s rdy p0 4 p0 3 p0 2 p0 1 p0 0 p4 3 p4 2 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 nc nc nc p1 4 /s in p1 3 / p1 1 p1 0 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p2 3 /in 3 p2 2 /in 2 p2 0 /in 0 v ref nc nc m37471m2-xxxfp m37471m4-xxxfp m37471e4-xxxfp m37471m8-xxxfp m37471e8-xxxfp outline 56p6n-a p5 1 /x cout v cc x in x out v ss av ss nc nc nc reset nc p5 0 /x cin t 1 p1 2 / t 0 note : the differences between 42p4b package type of 7471 group and 56p6n-a package type of 7471 group are package outline, power dissipation ability (absolute maximum ratings), and the provision of an av ss pin by the 56p6n-a package type. nc : no connection
3 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37470m2-xxxsp block diagram 14 15 18 17 16 v cc 13 24 23 22 21 20 19 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 p4(2) p3(4) p1(8) p0(8) cntr 0 cntr 1 int 1 int 0 4 v ss p2(4) clock generating circuit clock input x in clock output x out reset input reset rom 4096 bytes s i/o(8) pwm control a-d converter program counter pc h (8) program counter pc l (8) ram 128 bytes stack pointer s(8) processor status register ps (8) 8-bit arithmetic and logical unit index register y(8) index register x(8) accumu- lator a(8) instruction register (8) instruction decoder control signal timer 1 (8) timer 2 (8) timer 3 (8) timer 4 (8) i/o port p4 input port p3 v ref reference voltage input i/o port p2 i/o port p1 i/o port p0 (note 1) (note 2) data bus notes 1 : 8192 bytes for m37470m4/e4-xxxsp, and 16384 bytes for m37470m8/e8-xxxsp 2 : 192 bytes for m37470m4/e4-xxxsp, and 384 bytes for m37470m8/e8-xxxsp byte counter (4)
4 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37471m2-xxxsp block diagram 18 1 42 24 23 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 p5(4) p4(4) p3(4) p1(8) p0(8) cntr 0 cntr 1 x cin x cout int 1 int 0 8 p2(8) 19 20 x cin sub-clock input x cout sub-clock output 25 22 v cc v ss clock generating circuit main clock input x in main clock output x out reset input reset rom 4096 bytes s i/o(8) pwm control a-d converter program counter pc h (8) program counter pc l (8) ram 128 bytes stack pointer s(8) processor status register ps (8) 8-bit arithmetic and logical unit index register y(8) index register x(8) accumu- lator a(8) instruction register (8) instruction decoder control signal timer 1 (8) timer 2 (8) timer 3 (8) timer 4 (8) i/o port p4 input port p3 v ref reference voltage input i/o port p2 i/o port p1 i/o port p0 (note 1) (note 2) notes 1 : 8192 bytes for m37471m4/e4-xxxsp, and 16384 bytes for m37471m8/e8-xxxsp, m37471e8ss 2 : 192 bytes for m37471m4/e4-xxxsp, and 384 bytes for m37471m8/e8-xxxsp, m37471e8ss input port p5 data bus byte counter (4) 21
5 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37471m2-xxxfp block diagram 18 19 28 23 22 v cc 15 52 49 26 25 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 p5(4) p4(4) p3(4) p1(8) p0(8) cntr 0 cntr 1 x cin x cout int 1 int 0 8 51 21 v ss av ss p2(8) clock generating circuit reset input reset rom 4096 bytes s i/o(8) pwm control a-d converter program counter pc h (8) program counter pc l (8) ram 128 bytes stack pointer s(8) processor status register ps (8) index register y(8) index register x(8) accumu- lator a(8) instruction register (8) instruction decoder control signal timer 1 (8) timer 2 (8) timer 3 (8) timer 4 (8) i/o port p4 input port p3 v ref reference voltage input i/o port p2 i/o port p1 i/o port p0 (note 1) (note 2) notes 1 : 8192 bytes for m37471m4/e4-xxxfp, and 16384 bytes for m37471m8/e8-xxxfp 2 : 192 bytes for m37471m4/e4-xxxfp, and 384 bytes for m37471m8/e8-xxxfp input port p5 data bus x cin sub-clock input x cout sub-clock output main clock input x in main clock output x out byte counter (4) 8-bit arithmetic and logical unit
6 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functions of 7470/7471 group basic machine-language instructions instruction execution time clock input oscillation frequency memory size input/output port serial i/o timers a-d converter subroutine nesting interrupt clock generating circuit power source voltage power dissipation input/output characters operating temperature range device structure package input/output voltage output current m37470m2/m4/m8/e4/e8-xxxsp m37471m2/m4/m8/e4/e8-xxxsp m37471m2/m4/m8/e4/e8-xxxfp m37471e8ss functions 71 0.5 m s (the minimum instructions, at 8 mhz oscillation frequency) 8 mhz (max.) 4096 bytes 128 bytes 8192 bytes 192 bytes 16384 bytes 384 bytes 8-bit 5 2 8-bit 5 1 (4-bit 5 1 for 7470 group) 4-bit 5 2 (port p5 is not included in 7470 group) 4-bit 5 1 (2-bit 5 1 for 7470 group) 8-bit 5 1 8-bit timer 5 4 8-bit 5 1 (8 channels) (8-bit 5 1 (4 channels) for m37470m2/m4/m8) 64 level max. (m37470m2, m37471m2) 96 level max. (m37470m4/e4, m37471m4/e4) 192 level max. (m37470m8/e8, m37471m8/e8) 5 external interrupts, 6 internal interrupts, 1 software interrupt built-in circuit with internal feedback resistor (a ceramic or a quartz- crystal oscillator) 2.7 to 4.5 v (at 2.2v cc C2.0 mhz oscillation frequency), 4.5 to 5.5 v (at 8 mhz oscillation frequency) 35 mw (at 8 mhz oscillation frequency) 5 v C5 to 10 ma (p0, p1, p2, p4 : cmos tri-states) C20 to 85 c cmos silicon gate 32-pin shrink plastic molded dip 42-pin shrink plastic molded dip 56-pin plastic molded qfp 42-pin ceramic dip rom ram rom ram rom ram i/o i/o input i/o parameter m37470m2 m37471m2 m37470m4/e4 m37471m4/e4 m37470m8/e8 m37471m8/e8 p0, p1 p2 p3, p5 p4
7 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers input/ output pin description pin name functions power source voltage analog power source reset input clock input clock output reference voltage input i/o port p0 i/o port p1 i/o port p2 input port p3 i/o port p4 input port p5 input input output input i/o i/o i/o input i/o input notes 1 : av ss for m37471m2/m4/m8/e4/e8-xxxfp. 2 : only p2 0 Cp2 3 (in 0 Cin 3 ) 4-bit for 7470 group. 3 : only p4 0 and p4 1 2-bit for 7470 group. 4 : this port is not included in 7470 group. apply voltage of 2.7 to 5.5 v to v cc , and 0 v to v ss . ground level input pin for a-d converter. same voltage as v ss is applied. to enter the reset state, the reset input pin must be kept at l for 2 m s or more (under normal v cc conditions). these are i/o pins of internal clock generating circuit for main clock. to control generating frequency, an external ceramic or a quartz-crystal oscillator is connected between the x in and x out pins. if an external clock is used, the clock source should be connected the x in pin and the x out pin should be left open. feedback resistor is connected between x in and x out . reference voltage input pin for the a-d converter. port p0 is an 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. port p1 is an 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 4-bit. p1 2 , p1 3 are in common with timer output pins t 0 , t 1 , p1 4 , p1 5 , p1 6 , p1 7 are in common with serial i/o pins s in , s out , clk, s rdy , respec- tively. the output structure of s out and s rdy can be changed to n-channel open drain output. port p2 is an 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 4-bit. this port is in common with analog input pins in 0 Cin 7 . port p3 is a 4-bit input port. p3 0 , p3 1 are in common with external interrupt input pins int 0 , int 1 , and p3 2 , p3 3 are in common with timer input pins cntr 0 , cntr 1 . port p4 is a 4-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 4-bit. port p5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. p5 0 , p5 1 are in common with input/output pins of clock for clock function x cin , x cout . when p5 0 , p5 1 are used as x cin , x cout , connect a ceramic or a quartz-crystal oscillator between x cin and x cout . if an external clock input is used, connect the clock input to the x cin pin and open the x cout pin. feedback resistor is connected between x cin and x cout pins. v cc , v ss av ss (note 1) reset x in x out v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 (note 2) p3 0 Cp3 3 p4 0 Cp4 3 (note 3) p5 0 Cp5 3 (note 4)
8 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 7470/7471 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine in- structions or the series 740 users manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the mul, div, wit, and stp instruction can be used. cpu mode register the cpu mode register is allocated at address 00fb16. this register contains the stack page selection bit. fig. 1 structure of cpu mode register these bits must always be set to ?? p5 0 , p5 1 /x cin , x cout selection bit (note 2) 0 : p5 0 , p5 1 1 : x cin , x cout x cout drive capacity selection bit (note 2) 0 : low 1 : high clock (x in -x out ) stop bit (note 2) 0 : oscillates 1 : stops internal system clock selection bit (note 2) 0 : x in -x out selected (normal mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (address 00fb 16 ) b7 b0 stack page selection bit (note 1) 0 : in page 0 area 1 : in page 1 area 1 : in the m37470m2, m37470m4/e4, m37471m2, m37471m4/e4, set this bit to ?? 2 : in the 7470 group, set this bit to ?? notes
9 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers memory ? special function register (sfr) area the special function register (sfr) area contains the registers relating to functions such as i/o ports and timers. ? ram ram is used for data storage as well as a stack area. ? rom rom is used for storing user programs as well as the interrupt vector area. ? interrupt vector area the interrupt vector area is for storing jump destination ad- dresses used at reset or when an interrupt is generated. ? zero page zero page addressing mode is useful because it enables access to this area with fewer instruction cycles. ? special page special page addressing mode is useful because it enables ac- cess to this area with fewer instruction cycles. fig. 2 memory map ram (192 bytes) for m37470m8/e8 m37471m8/e8 sfr area not used interrupt vector area 0000 16 zero page special page ram (128 bytes) for m37470m2 m37471m2 rom (16k bytes) for m37470m8/e8 m37471m8/e8 rom (8k bytes) for m37470m4/e8 m37471m4/e8 rom (4k bytes) for m37470m2 m37471m2 ram (192 bytes) for m37470m4/e4 m37470m8/e8 m37471m4/e4 m37471m8/e8 not used 007f 16 00bf 16 00ff 16 0100 16 01bf 16 c000 16 e000 16 f000 16 ff00 16 ffea 16 ffff 16
10 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 3 sfr (special function register) memory map 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 00fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 port p0 port p0 direction register port p1 port p1 direction register port p2 port p2 direction register port p3 port p4 port p4 direction register port p5 (note 1) edge polarity selection register input latch register a-d control register a-d conversion register p0 pull-up control register p1?5 pull-up control register (note 2) timer 1 timer 2 timer 3 timer 4 timer ff register timer 12 mode register timer 34 mode register timer mode register 2 cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 notes 1 : this address is not used in the 7470 group. 2 : this address is allocated p1?4 pull-up control register for the 7470 group. serial i/o mode register serial i/o register serial i/o counter byte counter
11 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts interrupts can be caused by 12 different sources consisting of five external, six internal, and one software sources. interrupts are vectored interrupts with priorities shown in table 1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, the registers are pushed, interrupt disable flag i is set, and the program jumps to the address speci- fied in the vector table. the interrupt request bit is cleared automatically. the reset and brk instruction interrupt can never be disabled. other interrupts are disabled when the interrupt dis- able flag is set. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. external interrupts int 0 and int 1 can be asserted on either the falling or rising edge as set in the edge polarity selection register. when 0 is set to this register, the interrupt is activated on the falling edge; when 1 is set to the register, the interrupt is activated on the rising edge. when the device is put into power-down state by the stp instruc- tion or the wit instruction, if bit 5 in the edge polarity selection register is 1, the int 1 interrupt becomes a key on wake up inter- rupt. when a key on wake up interrupt is valid, an interrupt request is generated by applying the l level to any pin in port p0. in this case, the port used for interrupt must have been set for the input mode. if bit 5 in the edge polarity selection register is 0 when the device is in power-down state, the int 1 interrupt is selected. also, if bit 5 in the edge polarity selection register is set to 1 when the device is not in a power-down state, neither key on wake up interrupt re- quest nor int 1 interrupt request is generated. the cntr 0 /cntr 1 interrupts function in the same as int 0 and int 1 . the interrupt input pin can be specified for either cntr 0 or cntr 1 pin by setting bit 4 in the edge polarity selection register. figure 4 shows the structure of the edge polarity selection regis- ter, interrupt request registers 1 and 2, and interrupt control registers 1 and 2. interrupts other than the brk instruction interrupt and reset are accepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be reset with a program, but not set. the interrupt enable bit can be set and reset with a program. reset is treated as a non-maskable interrupt with the highest pri- ority. figure 5 shows interrupts control. interrupt source reset int 0 interrupt int 1 interrupt or key on wake up interrupt cntr 0 interrupt or cntr 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt serial i/o interrupt a-d conversion completion interrupt brk instruction interrupt priority 1 2 3 4 5 6 7 8 9 10 11 vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 remarks non-maskable external interrupt (polarity programmable) external interrupt (int 1 is polarity programmable) external interrupt (polarity programmable) non-maskable software interrupt table 1. interrupt vector address and priority
12 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 5 interrupt control fig. 4 structure of registers related to interrupt b7 b0 edge polarity selection register (eg) (address 00d4 16 ) int 0 edge selection bit int 1 edge selection bit cntr 0 edge selection bit cntr 1 edge selection bit 0 : falling edge 1 : rising edge cntr 0 /cntr 1 interrupt selection bit 0 : cntr 0 1 : cntr 1 int 1 source selection bit (at power-down state) 0 : p3 1 /int 1 1 : p0 0 ?0 7 ??level (for key-on wake-up) nothing is allocated (the value is undefined at reading) b7 b0 interrupt request register 1 (address 00fc 16 ) timer 1 interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit timer 4 interrupt request bit nothing is allocated (the value is undefined at reading) serial i/o transmit interrupt request bit a-d conversion completion interrupt request bit b7 b0 interrupt control register 1 (address 00fe 16 ) timer 1 interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit timer 4 interrupt enable bit nothing is allocated (the value is undefined at reading) serial i/o receive interrupt enable bit a-d conversion completion interrupt enable bit b7 b0 interrupt request register 2 (address 00fd 16 ) int 0 interrupt request bit int 1 interrupt request bit nothing is allocated (the value is undefined at reading) cntr 0 or cntr 1 interrupt request bit 0 : no interrupt request 1 : interrupt requested b7 b0 interrupt control register 2 (address 00ff 16 ) int 0 interrupt enable bit int 1 interrupt enable bit nothing is allocated (the value is undefined at reading) cntr 0 or cntr 1 interrupt enable bit 0 : interrupt disable 1 : interrupt enabled interrupt request bit interrupt enable bit interrupt disable flag i brk instruction reset interrupt request
13 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timer the 7470/7471 group has four timers; timer 1, timer 2, timer 3, and timer 4. a block diagram of timer 1 through 4 is shown in figure 6. timer 1 can be operated in the timer mode, event count mode, or pulse output mode. timer 1 starts counting when bit 0 in the timer 12 mode register (address 00f8 16 ) is set to 0. the count source can be selected from the f(x in ) divided by 16, f(x cin ) divided by 16, f(x cin ), or event input from p3 2 /cntr 0 pin. do not select f(x cin ) as the count source in the 7470 group. when bit 1 and bit 2 in the timer 12 mode register are 0, f(x in ) divided by 16 or f(x cin ) divided by 16 is selected. selection between f(x in ) and f(x cin ) is done by bit 7 in the cpu mode register (address 00fb 16 ). when bit 1 in the timer 12 mode register is 0 and bit 2 is 1, f(x cin ) is selected. and, when bit 1 in the timer 12 mode register is 1, an event input from the cntr 0 pin is selected. event inputs are selected depending on bit 2 in the edge polarity selection register (address 00d4 16 ). when this bit is 0, the in- verted value of cntr 0 input is selected; when the bit is 1, cntr 0 input is selected. when bit 3 in the timer 12 mode register is set to 1, the p1 2 pin becomes timer output t 0 . when the direction register of p1 2 is set for the output mode at this time, the timer 1 overflow divided by 2 is output from t 0 . please set the initial output value in the following procedure. set 1 to bit 0 of the timer 12 mode register. (timer 1 count stop.) set 1 to bit 0 of the timer mode register 2. a set the output value to bit 0 of the timer ff register. ? set the count value to the timer 1. ? set 0 to bit 0 of the timer 12 mode register. (timer 1 count start.) timer 2 can only be operated in the timer mode. timer 2 starts counting when bit 4 in the timer 12 mode register is set to 0. the count source can be selected from the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(x in ) or f(x cin ), and timer 1 overflow. do not select f(x cin ) as the count source in the 7470 group. when bit 5 in the timer 12 mode register is 0, any of the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(x in ) or (x cin ) is selected. the divide ratio is se- lected according to bit 6 and bit 7 in the timer 12 mode register, and selection between f(x in ) and f(x cin ) is made according to bit 7 in the cpu mode register. when bit 5 in the timer 12 mode reg- ister is 1, timer 1 overflow is selected as the count source. timer 3 can be operated in the timer mode, event count mode, or pwm mode. timer 3 starts counting when bit 0 in the timer 34 mode register (address 00f9 16 ) is set to 0. the count source can be selected from the f(x in ) divided by 16, f(x cin ) divided by 16, f(x cin ), timer 1 or timer 2 overflow, or an event input from p3 3 /cntr 1 pin according to the statuses of bit 1 and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg- ister 2 (address 00fa 16 ) and bit 7 in the cpu mode register. do not select f(x cin ) as the count source in the 7470 group. note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 3 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected re- gardless of the status of bit 6 in the timer mode register 2. event inputs are selected depending on bit 3 in the edge polarity selec- tion register. when this bit is 0, the inverted value of cntr 1 input is selected; when the bit is 1, cntr 1 input is selected. timer 4 can be operated in the timer mode, event count mode, pulse output mode, pulse width measuring mode, or pwm mode. timer 4 starts counting when bit 3 in the timer 34 mode register is set to 0 when bit 6 in this register is 0. when bit 6 is 1, the pulse width measuring mode is selected. the count source can be selected from timer 3 overflow, f(x in ) divided by 16, f(x cin ) divided by 16, f(x cin ), timer 1 or timer 2 overflow, or an event input from p3 3 /cntr 1 pin according to the statuses of bit 4 and bit 5 in the timer 34 mode register, bit 6 in the timer mode register 2, and bit 7 in the cpu mode register. do not select f(x cin ) as the count source in the 7470 group. note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 4 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. event inputs are selected depending on bit 3 in the edge polarity selection register. when this bit is 0, the inverted value of cntr 1 input is selected; when the bit is 1, cntr 1 input is selected. when bit 7 in the timer 34 mode register is set to 1, the p1 3 pin becomes timer output t 1 . when the direction register of p1 3 is set for the output mode at this time, the timer 4 overflow divided by 2 is output from t 1 when bit 7 in the timer mode register 2 is 0. please set the initial output value in the following procedure. set 1 to bit 3 of the timer 34 mode register. (timer 4 count stop.) set 1 to bit 1 of the timer mode register 2. a set the output value to bit 1 of the timer ff register. ? set the count value to the timer 4. ? set 0 to bit 3 of the timer 34 mode register. (timer 4 count start.) (1) timer mode timer performs down count operations with the dividing ratio being 1/(n+1). writing a value to the timer latch sets a value to the timer. when the value to be set to the timer latch is nn 16 , the value to be set to a timer is nn 16 , which is down counted at the falling edge of the count source from nn 16 to (nn 16 -1) to (nn 16 -2) to ...01 16 to 00 16 to ff 16 . at the falling edge of the count source immediately after timer value has reached ff 16 , value (nn 16 -1) obtained by subtracting one from the timer latch value is set (reloaded) to the timer to continue counting. at the rising edge of the count source immediately after the timer value has reached ff 16 , an overflow occurs and an interrupt request is generated.
14 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) event count mode timer operates in the same way as in the timer mode except that it counts input from the cntr 0 or cntr 1 pin. (3) pulse output mode in this mode, duty 50% pulses are output from the t 0 or t 1 pin. when the timer overflows, the polarity of the t 0 or t 1 pin output level is inverted. (4) pulse width measuring mode the 7470/7471 group can measure the h or l width of the cntr 0 or cntr 1 input waveform by using the pulse width mea- suring mode of timer 4. the pulse width measuring mode is selected by writing 1 to bit 6 in the timer 34 mode register. in the pulse width measuring mode, the timer counts the count source while the cntr 0 or cntr 1 input is h or l. whether the cntr 0 input or cntr 1 input to be measured can be specified by the sta- tus of bit 4 in the edge polarity selection register; whether the h width or l width to be measured can be specified by the status of bit 2 (cntr 0 ) and bit 3 (cntr 1 ) in the edge polarity selection reg- ister. (5) pwm mode the pwm mode can be entered for timer 3 and timer 4 by setting bit 7 in the timer mode register 2 to 1. in the pwm mode, the p1 3 pin is set for timer output t 1 to output pwm waveforms by setting bit 7 in the timer 34 mode register to 1. the direction register of p1 3 must be set for the output mode before this can be done. in the pwm mode, timer 3 is counting and timer 4 is idle while the pwm waveform is l. when timer 3 overflows, the pwm waveform goes h. at this time, timer 3 stops counting simultaneously and timer 4 starts counting. when timer 4 overflows, the pwm wave- form goes l, and timer 4 stops and timer 3 starts counting again. consequently, the l duration of the pwm waveform is deter- mined by the value of timer 3; the h duration of the pwm waveform is determined by the value of timer 4. when a value is written to the timer in operation during the pwm mode, the value is only written to the timer latch, and not written to the timer. in this case, if the timer overflows, a value one less the value in the timer latch is written to the timer. when any value is written to an idle timer, the value is written to both the timer latch and the timer. in this mode, do not select timer 3 overflow as the count source for timer 4. input latch function the 7470/7471 group can latch the p3 0 /int 0 , p3 1 /int 1 , p3 2 / cntr 0 , and p3 3 /cntr 1 pin level into the input latch register (ad- dress 00d6 16 ) when timer 4 overflows. the polarity of each pin latched to the input latch register can be selected by using the edge polarity selection register. when bit 0 in the edge polarity se- lection register is 0, the inverted value of the p3 0 /int 0 pin level is latched; when the bit is 1, the p3 0 /int 0 pin level is latched as it is. when bit 1 in the edge polarity selection register is 0, the in- verted value of the p3 1 /int 1 pin level is latched; when the bit is 1, the p3 1 /int 1 pin level is latched as it is. when bit 2 in the edge polarity selection register is 0, the inverted value of the p3 2 / cntr 0 pin level is latched; when the bit is 1, the p3 2 /cntr 0 pin level is latched as it is. when bit 3 in the edge polarity selection register is 0, the inverted value of the p3 3 /cntr 1 pin level is latched; when the bit is 1, the p3 3 /cntr 1 pin level is latched as it is.
15 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers mitsubishi microcomputers fig. 6 block diagram of timer 1 through 4 timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) 1/4 1/8 1/16 timer 3 latch (8) timer 3 (8) timer 4 latch (8) timer 4 (8) data bus t12m 2 t12m 0 t12m 1 tm2 0 1/2 1/2 1/2 1/8 eg 2 port latch t12m 3 t12m 6 t12m 7 t12m 5 t12m 4 tm2 6 t34m 1 t34m 2 t34m 0 t34m 4 t34m 5 f/f 1/2 tm2 1 tm2 7 eg 3 eg 2 t34m 3 t34m 6 eg 4 port latch x cin (note 1) x in p3 2 /cntr 0 p1 2 /t 0 p3 3 /cntr 1 p1 3 /t 1 t34m 7 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 eg 1 eg 0 timer 1 interrupt request timer 2 interrupt request timer 3 interrupt request timer 4 interrupt request c d3 q3 d2 q2 d1 q1 d0 q0 eg 3 cm 7 ( select gate : at reset, shaded side is connected.) note 1 : the 7470 group does not have x cin input.
16 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 7 structure of timer mode registers timer 1 count stop bit 0 : count start 1 : count stop timer 1 count source selection bit 0 : internal clock (note 1) 1 : p3 2 /cntr 0 external clock timer 1 internal clock source selection bit (note 2) 0 : f(x in ) divided by 16 or f(x cin ) divided by 16 1 : f(x cin ) p1 2 /t 0 port output selection bit 0 : p1 2 port output 1 : timer 1 overflow divided by 2 timer 2 count stop bit 0 : count start 1 : count stop timer 2 count source selection bit 0 : internal clock 1 : timer 1 overflow timer 2 internal clock source selection bits (note 3) 00 : f(x in ) divided by 16 or f(x cin ) divided by 16 01 : f(x in ) divided by 64 or f(x cin ) divided by 64 10 : f(x in ) divided by 128 or f(x cin ) divided by 128 11 : f(x in ) divided by 256 or f(x cin ) divided by 256 b7 b0 timer 1 overflow ff set enable bit 0 : set disable 1 : set enable timer 4 overflow ff set enable bit 0 : set disable 1 : set enable nothing is allocated (the value is undefined at reading) timer 3, timer 4 count overflow signal selection bit 0 : timer 1 overflow 1 : timer 2 overflow timer 3, timer 4 function selection bit 0 : normal mode 1 : pwm mode b7 b0 timer 3 count stop bit 0 : count start 1 : count stop timer 3 count source selection bits (note 3) 00 : f(x in ) divided by 16 or f(x cin ) divided by 16 01 : f(x cin ) 10 : timer 1 overflow or timer 2 overflow 11 : p3 3 /cntr 1 external clock timer 4 count stop bit 0 : count start 1 : count stop timer 4 count source selection bits (note 3) 00 : timer 3 overflow 01 : f(x in ) divided by 16 or f(x cin ) divided by 16 10 : timer 1 overflow or timer 2 overflow 11 : p3 3 /cntr 1 external clock timer 4 pulse width measuring mode selection bit 0 : timer mode 1 : pulse width measuring mode p1 3 /t 1 port output selection bit 0 : p1 3 port output 1 : timer 4 overflow divided by 2 or pwm output b7 b0 1 : f(x in ) divided by 16 in the 7470 group. 2 : the 7470 group does not use this bit (bit 2). set this bit to ?? 3 : do not select f(x cin ) as the count source in the 7470 group. timer mode register 2 (tm2) (address 00fa 16 ) timer 12 mode register (t12m) (address 00f8 16 ) timer 34 mode register (t34m) (address 00f9 16 ) notes
17 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o the block diagram of serial i/o is shown in figure 8. in the serial i/o mode, the receive ready signal (s rdy ), synchronous input/out- put clock (clk), and the serial i/o (s out , s in ) pins are used as p1 7 , p1 6 , p1 5 , and p1 4 , respectively. the serial i/o mode register (address 00dc 16 ) is an 8-bit register. bit 2 of this register is used to select a synchronous clock source. when this bit is 0, an external clock from p1 6 is selected. when this bit is 1, an internal clock is selected. the internal clock can be selected from among the divide by 8, di- vide by 16, divide by 32, divide by 512 frequency of the oscillator frequency f(x in ) or f(x cin ). do not select f(x cin ) as the count source in the 7470 group. the divide ratio is selected according to bit 0 and bit 1 in the serial i/o mode register, and selection be- tween f(x in ) and f(x cin ) is mode according to bit 7 in the cpu mode register. bits 3 and 4 decide whether parts of p1 will be used as a serial i/o or not. when bit 3 is 1, p1 6 becomes an i/o pin of the syn- chronous clock. when an internal synchronous clock is selected, the clock is output from p1 6 . if the external synchronous clock is selected, the clock is input to p1 6 . and p1 5 will be a serial output. to use p1 4 as a serial input, set the direction register bit which corresponds to p1 4 , to 0. for more information on the direction register, refer to the i/o pin sec- tion. fig. 8 block diagram of serial i/o 1/2 1/2 1/4 x cin (note 1) x in cm 7 counter 1/2 1/4 1/64 sm 1 sm 0 sm 5 sm 2 sync. circuit serial i/o counter (3) byte counter (4) serial i/o register (8) data bus clk input clk output s in s out s r sc sm 6 serial i/o interrupt request note 1 : the 7470 group does not have x cin input. sa rdy s rdy q ( select gate : at reset, shaded side is connected.)
18 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers bit 4 determines if p1 7 is used as an output pin for the receive ready signal (bit 4=1, s rdy ) or used as a normal i/o pin (bit 4=0). when the p1 7 pin is used as the s rdy output pin, output signal can be selected between s rdy signal and sa rdy signal by using bit 5 in the serial i/o mode register. the s rdy signal is driven l by a signal written into the serial i/o register to inform that the de- vice is ready to receive. then, the s rdy signal is driven h on the first falling edge of the transfer clock. the sa rdy signal is driven h by a signal written into the serial i/o register, and driven l on the last rising edge of the transfer clock. the function of serial i/o differs depending on the clock source; external clock or internal clock. internal clock C the serial i/o counter is set to 7 when data is stored in the serial i/o register. at each falling edge of the transfer clock, serial data is output to p1 5 . during the rising edge of this clock, data can be input from p1 4 and the data in the serial i/o register will be shifted 1 bit. data is output starting with the lsb. after the transfer clock has counted 8 times, the serial i/o register will be empty and the transfer clock will remain at a high level. at this time the interrupt request bit will be set. external clock C if an external clock is used, the interrupt request bit will be set after the transfer clock has counted 8 times but the transfer clock will not stop. due to this reason, the external clock must be controlled from the outside. timing diagrams are shown in figure 9. fig. 9 serial i/o timing d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 synchronous clock transfer clock serial i/o register write signal serial i/o output s out serial i/o input s in interrupt request bit set receive ready signal s rdy
19 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 10 structure of serial i/o mode register byte specify mode the serial i/o has a byte specify mode that allows one specific byte data to be selected for transmission or reception when serial i/o circuits of two or more microcomputers are connected to send or receive data through one bus. the data to be sent or received can be specified by writing a value into the byte counter. the value written in the byte counter is decremented by one each time eight cycles of transfer clock are input. when the value in the byte counter becomes 0, serial transmission/reception is done by the next eight cycles of transfer clock. when the value in the byte counter is not 0, the output on the s out pin is driven h by the falling edge of the first transfer clock pulse to inhibit transmission/ reception. serial i/o interrupt requests are generated only when serial trans- mission/reception is done after the value in the byte counter is decremented to 0. when the sa rdy signal output is selected, the sa rdy signal is driven l by the last rising edge of the transfer clock after the value in the byte counter is decremented to 0. note that in the byte mode, an external clock must be used as the sync. clock for the purpose of the mode. b7 b0 serial i/o mode register (sm) (address 00dc 16 ) synchronous clock selection bit 0 : external clock 1 : internal clock internal clock selection bits 00 : f(x in ) or f(xc in ) divided by 8 01 : f(x in ) or f(xc in ) divided by 16 10 : f(x in ) or f(xc in ) divided by 32 11 : f(x in ) or f(xc in ) divided by 512 serial i/o port selection bit 0 : normal i/o port 1 : s out , clk pins note : do not select f(x cin ) as the count source in the 7470 group. serial i/o byte specify mode selection bit 0 : normal mode 1 : byte specify mode s rdy signal output selection bit 0 : normal i/o port 1 : s rdy signal output pin s rdy signal selection bit 0 : s rdy signal 1 : sa rdy signal p1 5 /s out, p1 7 /s rdy output structure selection bit 0 : cmos output 1 : n-channel open drain output
20 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter the a-d conversion uses an 8-bit successive comparison method. figure 11 shows a block diagram of the a-d conversion circuit. conversion is automatically carried out once started by the pro- gram. there are eight analog input pins which are shared with p2 0 to p2 7 of port p2 (only p2 0 to p2 3 4-bit for 7470 group. which ana- log inputs are to be a-d converted is specified by using bit 2 to bit 0 in the a-d control register (address 00d9 16 ). pins for inputs to be a-d converted must be set for input by setting the direction reg- ister bit to 0. bit 3 in the a-d control register is an a-d conversion end bit. this is 0 during a-d conversion; it is set to 1 when the conversion is terminated. therefore, it is possible to know whether a-d conversion is terminated by checking this bit. bit 4 in the a-d control register is a v ref connection selection bit. during a-d conversion, this bit must be set 1 for the ladder resis- tor and v ref pin to be connected; after the a-d conversion is terminated, this bit can be reset to 0 to separate the ladder resis- tor from the v ref pin. in this way, power consumption in the ladder resistor can be suppressed while no a-d conversion is performed. figure 13 shows the relationship between the contents of a-d control register and the selected input pins. the a-d conversion register (address 00da 16 ) contains informa- tion on the results of conversion, so that it is possible to know the results of conversion by reading the contents of this register. the following explains the procedure to execute a-d conversion. first, set values to bit 2 to bit 0 in the a-d control register to select the pins that you want to execute a-d conversion. next, clear the a-d conversion end bit to 0. when the above is done, a-d conversion is initiated. the a-d con- version is completed after an elapse of 50 machine cycles (12.5 m s when f(x in )= 8 mhz), the a-d conversion end bit is set to 1, and the interrupt request bit is set to 1. the results of conver- sion are contained in the a-d conversion register. fig. 11 a-d converter circuit comparator a-d control circuit switch tree ladder resistor a-d conversion completion interrupt request v ss (note 1) v ref 1 : av ss for m37471m2/m4/m8/e4/e8-xxxfp 2 : 7470 group does not have p2 4 /in 4 to p2 7 /in 7 pins. p2 0 /in 0 p2 1 /in 1 p2 2 /in 2 p2 3 /in 3 p2 4 /in 4 p2 5 /in 5 p2 6 /in 6 p2 7 /in 7 data bus a-d control register (address 00d9 16 ) bit 4 channel selector notes bit 0 a-d conversion register (address 00da 16 )
21 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 structure of a-d control register a-d control register (address 00d9 16 ) b7 note : do not select in 4 to in 7 in the 7470 group. this bit must be set to 0. nothing is allocated (the value is undefined at reading) a-d conversion end bit 0 : under conversion 1 : end conversion analog input selection bit s 000 : in 0 001 : in 1 010 : in 2 011 : in 3 100 : in 4 101 : in 5 110 : in 6 111 : in 7 (note) vref connection selection bit 0 : v ref is separated 1 : v ref is connected b0
22 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers key on wake up key on wake up is one way of returning from a power down state caused by the stp or wit instruction. if any terminal of port p0 has l level applied, after bit 5 of the edge polarity selection regis- ter (eg 5 ) is set to 1, an interrupt is generated and the microcomputer is returned to the normal operating state. a key matrix can be connected to port p0 and the microcomputer can be returned to a normal state by pushing any key. the key on wake up interrupt is common with the int 1 interrupt. when eg 5 is set to 1, the key on wake up function is selected. however, key on wake up cannot be used in the normal operating state. when the microcomputer is in the normal operating state, both key on wake up and int 1 are invalid. fig. 13 block diagram of interrupt input and key on wake up circuit p3 3 /cntr 1 p3 2 /cntr 0 p3 0 /int 0 p3 1 /int 1 p0 7 p0 1 eg 3 port p3 3 data read circuit cntr interrupt request signal port p3 2 data read circuit eg 0 port p3 0 data read circuit int 0 interrupt request signal port p3 1 data read circuit int 1 interrupt request signal cpu halt state signal port p0 data read circuit eg 1 eg 5 p0 0 pull-up control register direction register pull-up control register direction register pull-up control register direction register eg 2 noise eliminating circuit 1/2 1/2 x cin (p5 0 ) x in cm 7 eg 4 noise eliminating circuit ( select gate: at reset, shaded side is connected.) note : the 7470 group does not have x cin input.
23 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit the 7470/7471 group are reset according to the sequence shown in figure 15. it starts the program from the address formed by us- ing the content of address ffff 16 as the high order address and the content of the address fffe 16 as the low order address, when the reset pin is held at l level for no less than 2 m s while the power voltage is in the recommended operating condition and then returned to h level. the internal initializations following reset are shown in figure 16. example of reset circuit is figure 14. immediately after reset, timer 3 and timer 4 are connected, and counts the f(x in ) divided by 16. at this time, ff 16 is set to timer 3, and 07 16 is set to timer 4. the reset is cleared when timer 4 overflows. fig. 15 timing diagram at reset fig. 14 example of reset circuit fig. 16 internal state of microcomputer at reset reset v cc 7470/7471 group notes 1 : frequency relation of x in and f is f(x in )=2 f . 2 : the mark ??means that the address is changeable depending upon the previous state. 00, s 00, s-1 00, s-2 fffe ad h , ad l pc h pc l ps ad l x in f reset internal address data sync 32768 counts of f(x in ) reset address from the vector table reset ? ? ?? ffff ad h (1) port p0 direction register (c1 16 ) (2) port p1 direction register (c3 16 ) (3) port p2 direction register (c5 16 ) (4) port p4 direction register (c9 16 ) (5) p0 pull-up control register (d0 16 ) (6) p1?5 pull-up control register (note 1) (d1 16 ) (7) edge selection register (eg) (d4 16 ) (8) a-d control register (d9 16 ) (9) serial i/o mode register (sm) (dc 16 ) (10) timer 12 mode register (t12m) (f8 16 ) (11) timer 34 mode register (t34m) (f9 16 ) (12) timer mode register 2 (tm2) (fa 16 ) (13) cpu mode register (cm) (fb 16 ) (14) interrupt request register 1 (fc 16 ) (15) interrupt request register 2 (fd 16 ) (16) interrupt control register 1 (fe 16 ) (17) interrupt control register 2 (ff 16 ) (18) program counter (pc h ) (pc l ) (19) processor status register (ps) 00 16 00 16 0000 000000 0000 001000 00 00 000 0 000 00 0 000 000 00 0 000 000 1 00 16 00 16 00 16 00 16 1 : this address is allocated p1?4 pull-up control register for 7470 group. bit 6 is not used. 2 : since the contents of both registers other than those listed above (including timers and the serial i/o register) are undefined at reset, it is necessary to set initial values. address contents of address ffff 16 00 16 00 contents of address fffe 16 notes
24 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers i/o ports (1) port p0 port p0 is an 8-bit i/o port with cmos outputs. as shown in figure 2, p0 can be accessed as memory through zero page address 00c0 16 . port p0s direction register allows each bit to be programmed individually as input or output. the direction register (zero page address 00c1 16 ) can be programmed as input with 0, or as output with 1. when in the output mode, the data to be output is latched to the port latch and output. when data is read from the output port, the output pin level is not read, only the latched data of the port latch is read. there- fore, a previously output value can be read correctly even though the output voltage level has been shifted up or down. port pins set as input are in the high impedance state so the signal level can be read. when data is written into the input port, the data is latched only to the output latch and the pin still remains in the high impedance state. following the ex- ecution of stp or wit instruction, key matrix with port p0 can be used to generate the interrupt to bring the microcomputer back in its normal state. when this port is selected for input, pull-up transistor can be connected in units of 1-bit. (2) port p1 port p1 has the same function as port p0. p1 2 Cp1 7 serve dual functions, and the desired function can be selected by the program. when this port is selected for input, pull-up tran- sistor can be connected in units of 4-bit. (3) port p2 port p2 has the same function as port p0. in the 7470 group, this port is p2 0 Cp2 3 , a 4-bit i/o port. this port can also be used as the analog voltage input pins. when this port is se- lected for input, pull-up transistor can be connected in units of 4-bit. (4) port p3 port p3 is a 4-bit input port. (5) port p4 port p4 is a 4-bit i/o port and has basically the same func- tions as port p0. in the 7470 group, this port is p4 0 and p4 1 , a 2-bit i/o port. when this port is selected for input, pull-up transistor can be connected in units of 4-bit . (6) port p5 port p5 is a 4-bit input port and pull-up transistor can be con- nected in units of 4-bit. p5 0 and p5 1 are shared with clock generating circuit input/output pins. the 7470 group does not have this port. (7) int 0 pin (p3 0 /int 0 pin) this is an interrupt input pin, and is shared with port p3 0 . when h to l or l to h transition input is applied to this pin, the int 0 interrupt request bit (bit 0 of address 00fd 16 ) is set to 1. (8) int 1 pin (p3 1 /int 1 pin) this is an interrupt input pin, and is shared with port p3 1 . when h to l or l to h transition input is applied to this pin, the int 1 interrupt request bit (bit 1 of address 00fd 16 ) is set to 1. (9) counter input cntr 0 pin (p3 2 /cntr 0 pin) this is a timer input pin, and is shared with port p3 2 . when this pin is selected to cntr 0 or cntr 1 interrupt input pin and h to l or l to h transition input is applied to this pin, the cntr 0 or cntr 1 interrupt request bit (bit 2 of ad- dress 00fd 16 ) is set to 1. (10) counter input cntr 1 pin (p3 3 /cntr 1 pin) this is a timer input pin, and is shared with port p3 3 . when this pin is selected to cntr 0 or cntr 1 interrupt input pin and h to l or l to h transition input is applied to this pin, the cntr 0 or cntr 1 interrupt request bit (bit 2 of ad- dress 00fd 16 ) is set to 1.
25 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 17 block diagram of ports p0, p1 0 Cp1 3 direction register port latch interrupt control circuit port p0 data bus port p 0 port p1 3 data bus t34m 7 t 1 data bus port p1 2 data bus t12m 3 t 0 port p1 1 data bus ports p1 0 ?1 3 port latch port latch port latch port p1 0 data bus port latch direction register pull-up control register direction register pull-up control register direction register direction register t r 1 t r 2 t r 3 t r 4 t r 5 t r 1? r 5 are pull-up transistors
26 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 18 block diagram of ports p1 4 Cp1 7 port latch port p1 7 data bus s rdy port p1 6 data bus clk output port p1 5 data bus port p1 4 data bus data bus ports p1 4 Cp1 7 clk input port latch port latch port latch direction register direction register direction register direction register pull-up control register s in s out sm 3 sm 2 sm 3 sm 7 sm 7 sm 4 t r 6 t r 6Ct r 9 are pull-up transistors t r 7 t r 8 t r 9
27 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers multi- plexer a-d conversion circuit port p3 int 0 , int 1 cntr 0 , cntr 1 data bus port p3 pull-up control register * direction register port latch * : control in units of 4-bit (control in units of 2-bit for 7470 group) port p4 port p4 data bus data bus pull-up control register * direction register port latch * : control in units of 4-bit port p2 port p2 data bus data bus t r 10 t r 11 t r 10? r 11 are pull-up transistors fig. 19 block diagram of ports p2Cp4
28 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 20 block diagram of port p5 pull-up control register port p5 data bus data bus port p5 3 port p5 2 port p5 1 data bus cm 4 data bus cm 4 cm 4 x cin port p5 0 cm 4 data bus note : 7470 group does not have this port. t r 12? r 15 are pull-up transistors t r 12 t r 13 t r 14 t r 15
29 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the 7470 group has one internal clock generating circuit and 7471 group has two internal clock generating circuits. figure 25 shows a block diagram of the clock generating circuit. normally, the frequency applied to the clock input pin x in divided by two is used as the internal clock f . bit 7 of cpu mode register can be used to switch the internal clock f to 1/2 the frequency ap- plied to the clock input pin x cin in the 7471 group. figure 21, 22 show a circuit example using a ceramic resonator (or a quartz-crystal oscillator). use the manufacturers recom- mended values for constants such as capacitance which will differ depending on each oscillator. when using an external clock signal, input from the x in (x cin ) pin and leave the x out (x cout ) pin open. a circuit example is shown in figure 23, 24. the 7470/7471 group has two low power dissipation modes; stop and wait. the microcomputer enters a stop mode when the stp instruction is executed. the oscillator (both x in clock and x cin clock) stops with the internal clock f held at h level. in this case timer 3 and timer 4 are forcibly connected and ff 16 is automati- cally set in timer 3 and 07 16 in timer 4. although oscillation is restarted when an external interrupt is ac- cepted, the internal clock f remains in the h state until timer 4 overflows. in other words, the internal clock f is not supplied until timer 4 overflows. this is because when a ceramic or similar other oscillator is used, a finite time is required until stable oscillation is obtained after restart. the microcomputer enters an wait mode when the wit instruction is executed. the internal clock f stops at h level, but the oscilla- tor does not stop. f is re-supplied (wait mode release) when the microcomputer receives an interrupt. instructions can be executed immediately because the oscillator is not stopped. the interrupt enable bit of the interrupt used to reset the wait mode or the stop mode must be set to 1 before execut- ing the wit or the stp instruction. low power dissipation operation is also achieved when the x in clock is stopped and the internal clock f is generated from the x cin clock (30 m a typ. at f(x cin ) = 32 khz). this operation is only 7471 group. x in clock oscillation is stopped when the bit 6 of cpu mode register is set and restarted when it is cleared. however, the wait time until the oscillation stabilizes must be generated with a program when restarting. figure 27 shows the transition of states for the system clock. fig. 21 example of ceramic resonator circuit (7470 group) fig. 22 example of ceramic resonator circuit (7471 group) fig. 23 external clock input circuit (7470 group) fig. 24 external clock input circuit (7471 group) x in x out c out c in r d m37470m2-xxxsp x in x out c cout c cin r d m37471m2-xxxsp/fp x cin x cout c out c in r d x in x out m37470m2-xxxsp external oscillating circuit open v cc v ss x in x out m37471m2-xxxsp/fp x cin x cout open external oscillating circuit external oscillating circuit or external pulse open v cc v ss v cc v ss
30 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 25 block diagram of clock generating circuit fig. 26 structure of cpu mode register q r s q r s q r s q r s q r s x in x out 1/2 1/8 reset stp instruction reset interrupt disable flag i interrupt request stp instruction wit instruction internal clock f x cin 1/2 timer 4 timer 3 t34m 0 t34m 1 t34m 2 x cout cm 6 cm 7 cm 7 (note 1) notes 1 : refer to timer 3 of [figure 6 block diagram of timer 1 through 4] 2 : 7470 group does not have x cin input and x cout output. select gate : at reset, shaded side is connected b7 b0 cpu mode register (address 00fb 16 ) these bits must always be set to 0. stack page selection bit (note 1) 0 : in page 0 area 1 : in page 1 area nothing is allocated (the value is undefined at reading) s5 0 , p5 1 /x cin , x cout selection bit (note 2) 0 : p5 0 , p5 1 1 : x cin , x cout x cout drive capacity selection bit (note 2) 0 : low 1 : high clock (x in -x out ) stop bit (note 2) 0 : oscillates 1 : stops internal system clock selection bit (note 2) 0 : x in -x out selected (normal mode) 1 : x cin -x cout selected (low-speed mode) notes 1 : in the m37470m2, m37470m4/e4, m37471m2, m37471m4/e4, set this bit to 0. 2 : in the 7470 group, set this bit to 0.
31 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes 1 : latency time is automatically generated upon release from the stp instruction due to the connections of timer 3 and 4. 2 : when the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation to stabilize must be inserted by the program. f(x in ) oscillation f(x cin ) stop f stop timer operation stp instruction interrupt (note 1) cm 4 = 0 cm 5 = 0 cm 6 = 0 cm 7 = 0 reset wit instruction interrupt f(x in ) oscillation f(x cin ) stop p5 0 , p5 1 input f = f(x in )/2 f(x in ) stop f(x cin ) stop f stop f(x in ) oscillation f(x cin ) oscillation f stop timer operation stp instruction interrupt (note 1) wit instruction interrupt f(x in ) oscillation f(x cin ) oscillation f = f(x in )/2 f(x in ) stop f(x cin ) stop f stop cm 4 = 0 cm 5 = 1 cm 4 = 1 (note 2) f(x in ) oscillation f(x cin ) oscillation f stop timer operation stp instruction interrupt (note 1) wit instruction interrupt f(x in ) oscillation f(x cin ) oscillation f = f(x cin )/2 f(x in ) stop f(x cin ) stop f stop cm 7 = 0 (cm 5 = 0) cm 7 = 1 f(x in ) stop f(x cin ) oscillation f stop timer operation stp instruction interrupt (note 1) wit instruction interrupt f(x in ) stop f(x cin ) oscillation f = f(x cin )/2 f(x in ) stop f(x cin ) stop f stop cm 6 = 0 (note 2) cm 6 = 1 cm 5 = 1 cm5 = 1 fig. 27 transition of states for the system clock
32 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers power on reset clock x oscillation internal system clock start (x ? 1/2 ? f ) program start from reset vector normal program ? operating at f(x in ) clock for clock function x c oscillation start (cm 4 = 1, cm 5 = 1) latency time for oscillation to stabilize (by program) ? operating at f(x in ) x c clock power down (cm 5 : 1 ? 0) internal clock f source switching x ? x c (cm 7 : 0 ? 1) clock x halt (x c in operation) (cm 6 = 1) internal clock halt (wit instruction) timer 4 (clock count) overflow internal clock operation start (wit instruction released) clock processing routine ? operating at f(x cin ) internal clock halt (wit instruction) interrupts from int 0 , int 1 , cntr 0 /cntr 1 , timer 1, timer 2, timer 3, timer 4, serial i/o, key on wake up internal clock operation start (wit instruction released) program start from interrupt vector clock x oscillation start (cm 6 = 0) latency time for oscillation to stabilize (by program) ? operating at f(x cin ) internal clock f source switching (x c ? x) (cm 7 : 1 ? 0) normal program ? operating at f(x in ) < an example of flow for system > ? ? ? ? ? y ? ? ? ? ? t ? ? ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? ? ? t normal operation operation on the clock function only ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? t return from clock function
33 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers stp instruction preparation (pushing registers) timer 3, timer 4 interrupt disable x/16 or x c /16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source timer 3, timer 4 start counting values set to timer 3, timer 4 that do not cause timer 4 to overflow until stp instruction is executed interrupt for return from stp enabled timer 4 interrupt request bit cleared clock x and clock for clock function x c halt (stp instruction) ram backup status interrupts from int 0 , int 1 , cntr 0 /cntr 1 , timer 1, timer 2, serial i/o, key on wake up clock x and clock for clock function x c oscillation start timer 4 overflow (x/16 or x c /16 ? timer 3 ? timer 4) internal system clock start program start from interrupt vector normal program ram backup function ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? y ? ? ? ? ? ? ? t return from ram backup function
34 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers power source voltage inputs 2.7 to 5.5 v to v cc and 0 v to v ss . ground level input pin for a-d converter. same voltage as v ss is applied. to enter the reset state, the reset input pin must be kept at a l for 2 m s or more (under normal v cc conditions). connect to v ss . these are i/o pins of internal clock generating circuit for main clock. to control generating frequency, an external ceramic or a quartz-crystal oscillator is con- nected between the x in and x out pins. if an external clock is used, the clock source should be connected the x in pin and the x out pin should be left open. feedback resistor is connected between x in and x out . reference voltage input pin for the a-d converter. v ref works as ce input. port p0 is an 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. port p0 works as an 8-bit data bus (d 0 Cd 7 ). port p1 is an 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 4-bit. p1 2 , p1 3 are in common with timer output pins t 0 , t 1 . p1 4 , p1 5 , p1 6 , p1 7 are in common with serial i/o pins s in , s out , clk, s rdy , respectively. the output structure of s out and s rdy can be changed to n-channel open drain output. p1 1 Cp1 7 works as the 7-bit address input (a 4 Ca 10 ). p1 0 must be opened. port p2 is an 8-bit input port. this port is in common with analog input pins in 0 Cin 7. p2 0 Cp2 3 works as the lower 4-bit address input (a 0 Ca 3 ). p2 4 Cp2 7 must be opened. port p3 is a 4-bit input port. p3 0 , p3 1 are in common with external interrupt input pins int 0 , int 1 and p3 2 , p3 3 are in common with timer input pins cntr 0 , cntr 1 . p3 0 , p3 1 works as the 2-bit address input (a 11 , a 12 ). p3 2 works as oe input. connect to p3 3 to v pp when programming or verifying. port p4 is a 4-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistor can be connected in units of 4-bit. p4 0 , p4 1 works as the higher 2-bit address input (a 13 , a 14 ). p4 2 , p4 3 must be opened. port p5 is a 4-bit input port and pull-up transistor can be connected in units of 4- bit. p5 0 , p5 1 are in common with input/output pins of clock for clock function x cin , x cout . when p5 0 , p5 1 are used as x cin , x cout , connect a ceramic or a quartz- crystal oscillator between x cin and x cout . if an external clock input is used, con- nect the clock input to the x cin pin and open the x cout pin. feedback resistor is connected between x cin and x cout pins. open. power source analog power source reset input reset input clock input clock output reference voltage input select mode i/o port p0 data input/output d 0 Cd 7 i/o port p1 address input a 4 Ca 10 i/o port p2 address input a 0 Ca 3 input port p3 address input a 11 , a 12 select mode v pp input i/o port p4 address input a 13 , a 14 input port p5 v cc ,v ss av ss (note 1) reset x in x out v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 (note 2) p3 0 Cp3 3 p4 0 Cp4 3 (note 3) p5 0 Cp5 3 (note 4) single-chip /eprom single-chip /eprom single-chip eprom single-chip /eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom input input output input input i/o i/o i/o input i/o input input input i/o input input built-in prom type microcomputers pin description pin functions mode name input/ output notes 1 : av ss for m37471m2/m4/m8/e4/e8-xxxfp. 2 : only p2 0 Cp2 3 (in 0 Cin 3 ) 4-bit for the 7470 group. 3 : only p4 0 and p4 1 2-bit for the 7470 group. 4 : this port is not included in the 7470 group.
35 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers eprom mode the m37470e4/e8, m37471e4/e8 feature an eprom mode in ad- dition to its normal modes. when the reset signal level is low (l), the chip automatically enters the eprom mode. table 2 lists the correspondence between pins and figure 30 to 32 give the pin connection in the eprom mode. when in the eprom mode, ports p0, p1 1 Cp1 7 , p2 0 Cp2 3 , p3, p4 0 , p4 1 , v ref are used for the prom (equivalent to the m5l27256). when in this mode, the built- in prom can be written to or read from using these pins in the same way as with the m5l27256. the oscillator should be con- nected to the x in and x out pins, or external clock should be connected to the x in pin. table 2. pin function in eprom mode m37470e4/e8, m37471e4/e8 v cc p3 3 v ss ports p1 1 Cp1 7 , p2 0 Cp2 3 , p3 0 , p3 1 , p4 0 , p4 1 port p0 v ref p3 2 v cc v pp v ss address input m5l27256 v cc v pp v ss fig. 28 pin connection in eprom mode data i/o ce oe a 0 Ca 14 d 0 Cd 7 ce oe a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v ss ce d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 14 a 13 v pp a 12 a 11 v cc oe v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 28 29 30 31 32 m37471e4-xxxsp m37471e8-xxxsp m37471e8ss p1 7 /s rdy p1 6 /clk p1 5 /s out p1 4 /s in p1 3 / p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 reset v cc 17 26 25 24 23 22 18 19 20 21 27 33 35 36 37 38 39 40 41 42 34 p5 3 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p5 2 p5 1 /x cout p5 0 /x cin p4 3 p4 2 : same functions as m5l27256 t 1 p1 2 / t 0
36 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 29 pin connection in eprom mode fig. 30 pin connection in eprom mode : same functions as m5l27256 p0 6 p1 5 /s out p2 1 /in 1 17 28 27 26 25 24 23 22 21 20 19 18 56 45 46 47 48 49 50 51 52 53 54 55 44 43 42 29 30 31 32 33 34 35 36 37 38 39 40 41 1 2 3 16 15 14 13 12 11 10 9 8 7 6 5 4 p5 2 p0 7 p0 5 p5 3 p1 6 /s clk v ss nc nc nc p1 7 /s rdy p0 4 p0 3 p0 2 p0 1 p0 0 p4 3 p4 2 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 nc nc nc p1 4 /s in p1 3 / p1 1 p1 0 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p2 3 /in 3 p2 2 /in 2 p2 0 /in 0 v ref nc nc m37471e4-xxxfp m37471e8-xxxfp p5 1 /x cout v cc x in x out v ss av ss nc nc nc reset nc p5 0 /x cin t 1 p1 2 / t 0 d 4 d 3 d 2 d 1 d 0 a 14 a 13 v pp oe a 12 a 11 ce a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 d 5 d 6 d 7 v ss a 9 a 8 a 10 v cc v ss a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v ss ce d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 14 a 13 v pp a 12 a 11 v cc oe v ss : same functions as m5l27256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m37470e4-xxxsp m37470e8-xxxsp p1 7 /s rdy p1 6 /clk p1 5 /s out p1 4 /s in p1 3 / p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 p4 0 p3 3 /cntr 1 p3 2 /cntr 0 p3 1 /int 1 p3 0 /int 0 reset v cc t 1 p1 2 / t 0
37 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers caution : since the screening temperature is higher than storage temperature, never expose to 150 c exceeding 100 hours. read-out output disable programming programming verify program disable output floating input output floating v il v ih v ih v il v ih v cc v cc v pp v pp v pp v cc v cc v cc v cc v cc v il v il v il v ih v ih pin mode ce oe v pp v cc data i/o note : v il and v ih indicate a l and h input voltage, respectively. table 3. i/o signal in each mode prom reading and writing reading to read the prom, set the ce and oe pins to l level. input the address of the data (a 0 Ca 14 ) to be read and the data will be out- put to the i/o pins (d 0 Cd 7 ). the data i/o pins will be floating when either the ce or oe pin is in the h state. writing to write to the prom, set the oe pin to h level. the cpu will en- ter the program mode when v pp is applied to the v pp pin. the address to be written to is selected with pins a 0 Ca 14 , and the data to be written is input to pins d 0 Cd 7 . set the ce pin to l level to begin writing. notes on writing ? m37470e4, m37471e4 when using a prom programmer, the address range should be between 6000 16 and 7fff 16 . addresses 0000 16 to 5fff 16 can- not be written to or read from correctly. ? m37470e8, m37471e8 when using a prom programmer, the address range should be between 4000 16 and 7fff 16 . when data is written between ad- dresses 0000 16 and 7fff 16 , fill addresses 0000 16 to 3fff 16 with ff 16 . erasing data can only erased on the m37471e8ss ceramic package, which includes a window. to erase data on this chip, use an ultra- violet light source with a 2537 angstrom wave length. the minimum radiation power necessary for erasing is 15ws/cm 2 . notes on handling (1) sunlight and fluorescent light contain wave lengths capable of erasing data. for ceramic package types, cover the transpar- ent window with a seal (provided) when this chip is in use. however, this seal must not contact the lead pins. (2) before erasing, the glass should be cleaned and stains such as finger prints should be removed thoroughly. if these stains are not removed, complete erasure of the data could be pre- vented. (3) since a high voltage (12.5 v) is used to write data, care should be taken when turning on the prom programmers power. (4) for the programmable microcomputer (shipped in one time prom version), mitsubishi does not perform prom write test and screening in the assembly process and following pro- cesses. to improve reliability after write, performing write and test according to the flow below before use is recommended. writing with prom programmer verify test with prom programmer function check in target device screening (caution) (leave at 150 c for 40 hours)
38 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers programming notes (1) the frequency ratio of the timer is 1/(n+1). (2) the contents of the interrupt request bits are not modified im- mediately after they have been written. after writing to an interrupt request register, execute at least one instruction be- fore executing a bbc or bbs instruction. (3) to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instruction yield proper decimal results. after execut- ing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. (4) an nop instruction must be used after the execution of a plp instruction. (5) do not execute the stp instruction during a-d conversion. (6) in the m37470, set bit 0, bit 1, and bit 3Cbit 7 to 0 of the cpu mode register. (7) multiply/divide instructions the index x mode (t) and the decimal mode (d) flag do not affect the mul and div instruction. the execution of these instructions does not modify the con- tents of the processor status register. data required for mask ordering please send the following data for mask orders. (1) mask rom confirmation form (2) mark specification form (3) rom data ......................................................... eprom 3 sets
39 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37470m2/m4/m8-xxxsp, m37470e4/e8-xxxsp absolute maximum ratings power source voltage input voltage x in input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 3 , p4 0 , p4 1 , v ref , reset output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 , x out power dissipation operating temperature storage temperature v cc v i v i v o p d t opr t stg v v v v mw c c C0.3 to 7 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 1000 C20 to 85 C40 to 150 unit symbol parameter ratings conditions t a = 25 c all voltages are based on v ss . output transistors are cut off. recommended operating conditions (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c unless otherwise noted) power source voltage power source voltage h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 3 , reset, x in h input voltage p2 0 Cp2 3 , p4 0 , p4 1 l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 3 l input voltage p2 0 Cp2 3 , p4 0 , p4 1 l input voltage reset l input voltage x in h sum output current p0 0 Cp0 7 , p4 0 , p4 1 h sum output current p1 0 Cp1 7, p2 0 Cp2 3 l sum output current p0 0 Cp0 7 , p4 0 , p4 1 l sum output current p1 0 Cp1 7, p2 0 Cp2 3 h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 (note 2) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 (note 2) 2.7 4.5 0.8v cc 0.7v cc 0 0 0 0 v v v v v v v v ma ma ma ma ma ma ma ma 4.5 5.5 v cc v cc 0.2v cc 0.25v cc 0.12v cc 0.16v cc C30 C30 60 60 C10 20 C5 10 1 2 1 2 2.2v cc C 2.0 8 5 0 symbol parameter limits min. typ. max. unit f( cntr ) f( clk ) f(x in ) f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v mhz mhz mhz v cc v ss v ih v ih v il v il v il v il i oh(sum) i oh(sum) i ol(sum) i ol(sum) i oh(peak) i ol(peak) i oh(avg) i ol(avg) timer input frequency cntr 0 (p3 2 ), cntr 1 (p3 3 ) (note 1) clock input oscillation frequency (note 1) serial i/o clock input frequency s clk (p1 6 ) (note 1) f(x in ) = 2.2v cc C2.0 mhz f(x in ) = 8 mhz notes 1 : oscillation frequency is at 50% duty cycle. 2 : the average output current i oh (avg) and i ol (avg) are the average value during a 100 ms.
40 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37470m2/m4/m8-xxxsp, m37470e4/e8-xxxsp electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 1 C5 C3 C1.0 C0.35 C5 C3 C5 C3 C1.0 C0.35 C5 C3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 4 2 1 1 10 5.5 0.5 0.3 0.5 0.3 0.5 0.3 C0.5 C0.18 C0.5 C0.18 7 3.5 1.8 7.5 4 2 2 1 0.5 0.1 1 3 2 C0.25 C0.08 C0.25 C0.08 2 v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v t a = 25 c t a = 85 c v v v v v m a ma m a m a ma m a m a m a m a m a max. limits symbol parameter min. typ. unit test conditions ma ma ma m a v v ram ram retention voltage stop all oscillation f(x in )=8 mhz f(x in )=4 mhz f(x in )=8 mhz f(x in )=4 mhz f(x in )=8 mhz f(x in )=4 mhz at normal mode, a-d conversion is not executed. at normal mode, a-d conversion is executed. at wait mode. at stop mode, f(x in )=0, v cc =5 v i cc power source current v cc = 5 v, i oh = C5 ma v cc = 3 v, i oh = C1.5 ma v cc = 5 v, i ol = 10 ma v cc = 3 v, i ol = 3 ma v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v use as clk input v oh v ol v t+ C v tC v t+ Cv tC v t+ Cv tC i il i il i il i il i ih i ih i ih i ih h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 h input current reset, x in l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p4 0 , p4 1 hysteresis p0 0 C p0 7 , p3 0 C p3 3 hysteresis reset hysteresis p1 6 /clk l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 2 , p4 0 Cp4 1 l input current p3 3 l input current p2 0 Cp2 3 l input current reset, x in h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 2 , p4 0 , p4 1 h input current p3 3 h input current p2 0 Cp2 3 v i = 0 v, not use pull-up transistor v i = 0 v, use pull-up transistor v i = 0 v v i = 0 v, not use as analog input, not use pull-up transistor v i = 0 v, not use as analog input, use pull-up transistor v i = 0 v (x in is at stop mode) v i = v cc , not use pull-up transistor v i = v cc v i = v cc , not use as analog input, not use pull-up transistor v i = v cc , (x in is at stop mode)
41 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, f(x in )=4 mhz, unless otherwise noted) unit symbol parameter test conditions limits 8 2 0.9 2 3 4 7 25 12.5 v cc 10 v ref resolution non-linearity error differential non-linearity error zero transition error full-scale transition error conversion time reference input voltage ladder resistance value analog input voltage v cc = v ref = 5.12 v, i ol (sum) = 0 ma v cc = v ref = 3.072 v, i ol (sum) = 0 ma v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = 2.7 to 5.5 v, f(x in ) = 4 mhz v cc = 4.5 to 5.5 v, f(x in ) = 8 mhz 0.5v cc 2 0 5 max. typ. min. C C C v ot v fst t conv v ref r ladder v ia bits lsb lsb lsb lsb m s v k w v
42 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers m37471m2/m4/m8-xxxsp/fp, m37471e4/e8-xxxsp/fp, m37471e8ss absolute maximum ratings power source voltage input voltage x in i nput voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 0 Cp5 3 , v ref , reset output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 , x out power dissipation operating temperature storage temperature v cc v i v i v o p d t opr t stg v v v v mw c c C0.3 to 7 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 1000 (note 1) C20 to 85 C40 to 150 unit symbol parameter ratings conditions t a = 25 c note 1 : 500 mw for m37471m2/m4/m8-xxxfp. all voltages are based on v ss . output transistors are cut off. 4.5 5.5 v cc v cc 0.2v cc 0.25v cc 0.12v cc 0.16v cc C 30 C 30 60 60 C 10 20 C 5 10 1 2 1 2 2.2v cc C 2.0 8 50 f( cntr ) f( clk ) f(x in ) f(x cin ) recommended operating conditions (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = C20 to 85 c unless otherwise noted) 2.7 4.5 0.8v cc 0.7v cc 0 0 0 0 v v v v v v v v v ma ma ma ma ma ma ma ma 5 0 0 32 symbol parameter limits min. typ. max. unit f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v mhz mhz mhz khz v cc v ss av ss v ih v ih v il v il v il v il i oh(sum) i oh(sum) i ol(sum) i ol(sum) i oh(peak) i ol(peak) i oh(avg) i ol(avg) timer input frequency cntr 0 (p3 2 ), cntr 1 (p3 3 ) (note 3) main clock input oscillation frequency (note 3) serial i/o clock input frequency s clk (p1 6 ) (note 3) f(x in ) = 2.2v cc C 2.0 mhz f(x in ) = 8 mhz sub-clock input oscillation frequency for clock function (note 3, 4) notes 1 : it is except to use p5 0 as x cin . 2 : the average output current i oh (avg) and i ol (avg) are the average value during a 100 ms. 3 : oscillation frequency is at 50% duty cycle. 4 : when used in the low-speed mode, the clock oscillation frequency for clock function should be f(x cin ) < f(x in ) / 3. power source voltage power source voltage analog power source voltage h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 3 , reset, x in h input voltage p2 0 Cp2 7 , p4 0 Cp4 3 , p5 0 Cp5 3 (note 1) l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 3 l input voltage p2 0 Cp2 7 , p4 0 Cp4 3 , p5 0 Cp5 3 (note 1) l input voltage reset l input voltage x in h sum output current p0 0 Cp0 7 , p4 0 Cp4 3 h sum output current p1 0 Cp1 7 , p2 0 Cp2 7 l sum output current p0 0 Cp0 7 , p4 0 Cp4 3 l sum output current p1 0 Cp1 7 , p2 0 Cp2 7 h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 (note 2) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 (note 2)
43 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ma ma m a ma m a v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v t a = 25 c t a = 85 c f(x in )=8 mhz f(x in )=4 mhz f(x in )=8 mhz f(x in )=4 mhz f(x in )=8 mhz f(x in )=4 mhz m37471m2/m4/m8-xxxsp/fp, m37471e4/e8-xxxsp/fp, m37471e8ss electrical characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 1 C5 C3 C1.0 C0.35 C5 C3 C5 C3 C1.0 C0.35 C5 C3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 80 40 4 2 1 12 8 1 10 0.5 0.3 0.5 0.3 0.5 0.3 C0.5 C0.18 C0.5 C0.18 7 3.5 1.8 7.5 4 2 30 15 2 1 0.5 3 2 0.1 1 v cc = 5 v, i oh = C5 ma v cc = 3 v, i oh = C1.5 ma v cc = 5 v, i ol = 10 ma v cc = 3 v, i ol = 3 ma v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v max. limits symbol parameter min. typ. unit test conditions at normal mode, a-d conversion is not executed. 3 2 C0.25 C0.08 C0.25 C0.08 2 v v v v v m a ma m a m a ma m a m a m a m a m a v oh v ol v t+ C v tC v t+ Cv tC v t+ Cv tC i il i il i il i il i ih i ih i ih i ih stop all oscillation v ram ram retention voltage stop all oscillation v cc = 5 v at wait mode. at normal mode, a-d conversion is executed. i cc power source current at wait mode, x in = 0 hz, x cin = 32 khz, x cout is low-power mode, t a =25 c at low-speed mode, t a =25 c, f(x in )=0, f(x cin )=32 khz, x cout drive capacity is low, a-d conversion is not executed. h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 0 Cp4 3 hysteresis p0 0 Cp0 7 , p3 0 Cp3 3 hysteresis reset hysteresis p1 6 /clk l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 2 , p4 0 Cp4 3 , p5 0 Cp5 3 l input current p3 3 l input current reset, x in h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 2 , p4 0 Cp4 3 , p5 0 Cp5 3 h input current p3 3 h input current p2 0 Cp2 7 v i = 0 v, not use pull-up transistor v i = 0 v, use pull-up transistor v i = 0 v used as clk input v i = 0 v, not use as analog input, not use pull-up transistor v i = 0 v, not use as analog input, use pull-up transistor v i = 0 v (x in is at stop mode) v i = v cc , not use pull-up transistor v i = v cc v i = v cc , not use as analog input, not use pull-up transistor v i = v cc , (x in is at stop mode) l input current p2 0 Cp2 7 h input current reset, x in
44 7470/7471 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss =av ss = 0 v, t a = C20 to 85 c, f(x in) = 4 mhz, unless otherwise noted) unit symbol parameter test conditions limits 8 2 0.9 2 3 4 7 25 12.5 v cc 10 v ref resolution non-linearity error differential non-linearity error zero transition error full-scale transition error conversion time reference input voltage ladder resistance value analog input voltage v cc = v ref = 5.12 v, i ol (sum) = 0 ma v cc = v ref = 3.072 v, i ol (sum) = 0 ma v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = 2.7 to 5.5 v, f(x in ) = 4 mhz v cc = 4.5 to 5.5 v, f(x in ) = 8 mhz 0.5v cc 2 0 5 max. typ. min. C C C v ot v fst t conv v ref r ladder v ia bits lsb lsb lsb lsb m s v k w v
? 1998 mitsubishi electric corp. new publication, effective jan. 1998. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers 7470/7471 group single-chip 8-bit cmos microcomputer
rev. rev. no. date 1.0 first edition 980110 revision description list 7470/7471 group data sheet (1/1) revision description

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